Tuesday, April 24, 2018

Investigation of a near mid-gap trap energy level in mid-wavelength infrared InAs/GaSb type-II superlattices

In this report, we present results of an experimental investigation of a near mid-gap trap energy level in InAs10 ML/GaSb10 ML type-II superlattices. Using thermal analysis of dark current, Fourier transform photoluminescence and low-frequency noise spectroscopy, we have examined several wafers and diodes with similar period design and the same macroscopic construction. All characterization techniques gave nearly the same value of about 140 meV independent of substrate type. Additionally, photoluminescence spectra show that the transition related to the trap centre is temperature independent. The presented methodology for thermal analysis of dark current characteristics should be useful to easily estimate the position of deep energy levels in superlattice photodiodes.

Source:IOPscience

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Wednesday, April 4, 2018

Selective area growth of III–V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices

We demonstrate a catalyst-free growth technique to directly integrate III–V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs–InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5–6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core–shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III–V based electronic and optoelectronic devices on silicon.

Source:IOPscience

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